Recently there has been an interest in fabricating memories having memory cells disposed at numerous levels above a substrate. Each level includes a plurality of spaced-apart first lines extending in one direction, which lines are vertically separated from a plurality of parallel spaced-apart second lines in a second direction, for example, extending perpendicular to the first lines. Memory cells are disposed between the first lines and second lines at the intersections (or the projection thereof) of these lines.
Exemplary memory arrays are described, for example, in U.S. Pat. Nos. 5,835,396 and 6,034,882, which describe a pillar style of memory cell, each formed between an associated first array line and an associated second array line. Characteristic of such pillar style memory cells is the separation of the various structures forming each cell from similar structures forming adjacent cells.
Another way of fabricating three-dimensional memory arrays departs from the structures shown in these patents and uses “rail-stacks” to form the memory cells. A rail stack is formed by creating successive layers of material, which are then etched together to form an aligned stack of layers. A memory cell may be formed at the intersection of two such rail stacks. Fabricating a memory array using rail stacks frequently requires fewer mask layers (and processing steps) to implement the array.
Exemplary memory arrays utilizing rail stacks are described in U.S. patent application Ser. No. 09/560,626 by N. Johan Knall, filed Apr. 28, 2000, which application describes a memory employing antifuses where a diode is formed upon programming a particular bit. In this connection see, “A Novel High-Density Low-Cost Diode Programmable Read Only Memory,” by de Graaf, Woerlee, Hart, Lifka, de Vreede, Janssen, Sluijs and Paulzen, IEDM-96, beginning at page 189 and U.S. Pat. Nos. 4,876,220; 4,881,114 and 4,543,594.